Low-power H.264/AVC baseline decoder for portable applications

Ke Xu; Chiu Sing Choy

doi:10.1145/1283780.1283835

Low-power H.264/AVC baseline decoder for portable applications

Ke Xu^*
, Chiu Sing Choy

^*Corresponding author for this work

Chinese University of Hong Kong

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

14 Scopus citations

Abstract

In this paper, we propose a low-power H.264/AVC baseline decoder. A systematic methodology for power reduction at all design levels for video decoding is proposed and applied. Power consumption is optimized at algorithm, architecture, circuit, and physical levels. The VLSI implementation results show that with UMC 180nm technology, the proposed design is able to decode QCIF 30fps at 1.5MHz. It consumes 698W operated under 1.8V power supply. The decoder contains 169k logic gates and 2.5KB on-chip SRAM. The total chip area is 4.4x4.4mm2 in a CQFP 208 package. The low-power and real-time features make our design ideal for portable applications where video quality is often traded off for energy.

Original language	English
Title of host publication	ISLPED'07
Subtitle of host publication	Proceedings of the 2007 International Symposium on Low Power Electronics and Design
Pages	256-261
Number of pages	6
DOIs	https://doi.org/10.1145/1283780.1283835
State	Published - 2007
Externally published	Yes
Event	ISLPED'07: 2007 International Symposium on Low Power Electronics and Design - Portland, OR, United States Duration: 27 Aug 2007 → 29 Aug 2007

Publication series

Name	Proceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)	1533-4678

Conference

Conference	ISLPED'07: 2007 International Symposium on Low Power Electronics and Design
Country/Territory	United States
City	Portland, OR
Period	27/08/07 → 29/08/07

Keywords

Decoder
H.264/AVC
Low-power

Access to Document

10.1145/1283780.1283835

Cite this

@inproceedings{d4769f714788456894d6ba8d370de5f4,

title = "Low-power H.264/AVC baseline decoder for portable applications",

abstract = "In this paper, we propose a low-power H.264/AVC baseline decoder. A systematic methodology for power reduction at all design levels for video decoding is proposed and applied. Power consumption is optimized at algorithm, architecture, circuit, and physical levels. The VLSI implementation results show that with UMC 180nm technology, the proposed design is able to decode QCIF 30fps at 1.5MHz. It consumes 698W operated under 1.8V power supply. The decoder contains 169k logic gates and 2.5KB on-chip SRAM. The total chip area is 4.4x4.4mm2 in a CQFP 208 package. The low-power and real-time features make our design ideal for portable applications where video quality is often traded off for energy.",

keywords = "Decoder, H.264/AVC, Low-power",

author = "Ke Xu and Choy, \{Chiu Sing\}",

year = "2007",

doi = "10.1145/1283780.1283835",

language = "英语",

isbn = "1595937099",

series = "Proceedings of the International Symposium on Low Power Electronics and Design",

pages = "256--261",

booktitle = "ISLPED'07",

note = "ISLPED'07: 2007 International Symposium on Low Power Electronics and Design ; Conference date: 27-08-2007 Through 29-08-2007",

}

Xu, K & Choy, CS 2007, Low-power H.264/AVC baseline decoder for portable applications. in ISLPED'07: Proceedings of the 2007 International Symposium on Low Power Electronics and Design. Proceedings of the International Symposium on Low Power Electronics and Design, pp. 256-261, ISLPED'07: 2007 International Symposium on Low Power Electronics and Design, Portland, OR, United States, 27/08/07. https://doi.org/10.1145/1283780.1283835

Low-power H.264/AVC baseline decoder for portable applications. / Xu, Ke; Choy, Chiu Sing.
ISLPED'07: Proceedings of the 2007 International Symposium on Low Power Electronics and Design. 2007. p. 256-261 (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Low-power H.264/AVC baseline decoder for portable applications

AU - Xu, Ke

AU - Choy, Chiu Sing

PY - 2007

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N2 - In this paper, we propose a low-power H.264/AVC baseline decoder. A systematic methodology for power reduction at all design levels for video decoding is proposed and applied. Power consumption is optimized at algorithm, architecture, circuit, and physical levels. The VLSI implementation results show that with UMC 180nm technology, the proposed design is able to decode QCIF 30fps at 1.5MHz. It consumes 698W operated under 1.8V power supply. The decoder contains 169k logic gates and 2.5KB on-chip SRAM. The total chip area is 4.4x4.4mm2 in a CQFP 208 package. The low-power and real-time features make our design ideal for portable applications where video quality is often traded off for energy.

AB - In this paper, we propose a low-power H.264/AVC baseline decoder. A systematic methodology for power reduction at all design levels for video decoding is proposed and applied. Power consumption is optimized at algorithm, architecture, circuit, and physical levels. The VLSI implementation results show that with UMC 180nm technology, the proposed design is able to decode QCIF 30fps at 1.5MHz. It consumes 698W operated under 1.8V power supply. The decoder contains 169k logic gates and 2.5KB on-chip SRAM. The total chip area is 4.4x4.4mm2 in a CQFP 208 package. The low-power and real-time features make our design ideal for portable applications where video quality is often traded off for energy.

KW - Decoder

KW - H.264/AVC

KW - Low-power

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M3 - 会议稿件

AN - SCOPUS:36949040796

SN - 1595937099

SN - 9781595937094

T3 - Proceedings of the International Symposium on Low Power Electronics and Design

SP - 256

EP - 261

BT - ISLPED'07

T2 - ISLPED'07: 2007 International Symposium on Low Power Electronics and Design

Y2 - 27 August 2007 through 29 August 2007

ER -

Low-power H.264/AVC baseline decoder for portable applications

Abstract

Publication series

Conference

Keywords

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