Low power deterministic test pattern generator based on non-uniform cellular automata using dynamical extend algorithm

The test pattern generator (TPG) in deterministic BIST often suffered from problems during the synthesis, such as depending on redundant test patterns, and resulting in extra test power consumption and idle test cycles. An efficient algorithm was proposed to synthesize a built-in TPG from low power deterministic test patterns without inserting any redundancy test vectors. The structure of TPG was based on the non-uniform cellular automata (CA) and was used to test combinational circuits. The key idea of algorithm was to dynamically extend the neighborhood based on simulated annealing for finding the optimal non-uniform CA topology. Simulation results on benchmark combinational circuits showed that the proposed algorithm is efficient in synthesizing low power deterministic TPGs, with no effects on fault coverage and test time.