Low-power data bus FV-BI adaptive coding based on time division multiplexing technique

By combining the advantage of the improved frequent value (FV) and bus invert (BI) coding techniques, the FV-BI adaptive bus coding is proposed, which mainly uses time division multiplexing technique to solve multiple sets of data bus coding and two additional data line problems. Experiment results show that FV-BI coding yields a 22%-53% reduction in data bus switching activity for benchmark programs in addition picture, audio/video and random testing data. Moreover the reduction in switching activity by FV-BI is 2-4 times the reduction achieved by BI and FV alone. Meanwhile the power estimation of system level and sign-off level by Mat-lab and PrimePower program in 0.18 μm process technology is given. The results in 10 mm interconnect length show that the FV-BI adaptive coding technique can effectively reduce the power of chip. Finally, the FV, BI and FV-BI coding techniques are implemented in field programmable gate array (FPGA) and evaluate the power based on Xpower program and board testing. The results also show that FV-BI coding scheme is effectively reduced the power of interconnect system.