Skip to main navigation Skip to search Skip to main content

Low-power crosstalk avoidance encoding for on-chip data buses

  • Qingli Zhang*
  • , Jinxiang Wang
  • , Yizheng Ye
  • *Corresponding author for this work
  • Harbin Institute of Technology

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The power consumption and propagation delay are two important issues for global on-chip buses in deep submicron System-on-Chip design. And inter-wire coupling is a major source of the two issues. In this paper, we present a new bus encoding scheme for generic on-chip data buses that simultaneously reduces coupling power consumption and eliminates capacitive crosstalk. Experimental results indicate that our proposed scheme can provide about 21% bus power reduction on average while minimizing the crosstalk delay. Furthermore, we employ a bus-invert coding technique to improve the power efficiency of the proposed approach by up to 7.7%.

Original languageEnglish
Title of host publicationAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Pages1611-1614
Number of pages4
DOIs
StatePublished - 2006
EventAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - , Singapore
Duration: 4 Dec 20066 Dec 2006

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

ConferenceAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Country/TerritorySingapore
Period4/12/066/12/06

Keywords

  • Coulping
  • Encoding
  • Low-power
  • On-chip bus

Fingerprint

Dive into the research topics of 'Low-power crosstalk avoidance encoding for on-chip data buses'. Together they form a unique fingerprint.

Cite this