IPRM: IP core resource multiplexing of core wrapper design for reducing test application time in DVFS-based multicore SoCs

Libao Deng; Baoquan Zhang; Sha Wang; Chengyu Jin

doi:10.1016/j.vlsi.2016.12.011

IPRM: IP core resource multiplexing of core wrapper design for reducing test application time in DVFS-based multicore SoCs

Libao Deng^*
, Baoquan Zhang
, Sha Wang
, Chengyu Jin

^*Corresponding author for this work

School of Information Science and Engineering, Harbin Institute of Technology Weihai
Harbin Institute of Technology

Research output: Contribution to journal › Article › peer-review

Abstract

A modify wrapper/test access mechanism(TAM) structure is described to explore the maximal potential capacity of TAM, named “IP cores resource multiplexing(IPRM)”, reducing test application time for DVFS-based multicore System-on-Chips(MSoCs). The IPRM core wrappers, different from standard wrappers, enable to isolated core wrapper resource again to store test data for embedded cores under test. An integer linear programming (ILP) formulation with IPRM wrapper is proposed to improve multi-site test. Experimental results of the ITC’02 SoC Benchmark show that IPRM core wrapper reduces the burdens on ATE effectively, and can reduce the test application time by 10–50%.

Original language	English
Pages (from-to)	132-146
Number of pages	15
Journal	Integration
Volume	57
DOIs	https://doi.org/10.1016/j.vlsi.2016.12.011
State	Published - 1 Mar 2017
Externally published	Yes

Keywords

DVFS
Design for testability
IP core resource multiplexing
Multicore SoC testing
Wrapper structure design

Access to Document

10.1016/j.vlsi.2016.12.011

Cite this

@article{fb4ded2d66ab47e2b204d3505d5c10ee,

title = "IPRM: IP core resource multiplexing of core wrapper design for reducing test application time in DVFS-based multicore SoCs",

abstract = "A modify wrapper/test access mechanism(TAM) structure is described to explore the maximal potential capacity of TAM, named {\textquotedblleft}IP cores resource multiplexing(IPRM){\textquotedblright}, reducing test application time for DVFS-based multicore System-on-Chips(MSoCs). The IPRM core wrappers, different from standard wrappers, enable to isolated core wrapper resource again to store test data for embedded cores under test. An integer linear programming (ILP) formulation with IPRM wrapper is proposed to improve multi-site test. Experimental results of the ITC{\textquoteright}02 SoC Benchmark show that IPRM core wrapper reduces the burdens on ATE effectively, and can reduce the test application time by 10{\textendash}50\%.",

keywords = "DVFS, Design for testability, IP core resource multiplexing, Multicore SoC testing, Wrapper structure design",

author = "Libao Deng and Baoquan Zhang and Sha Wang and Chengyu Jin",

note = "Publisher Copyright: {\textcopyright} 2017 Elsevier B.V.",

year = "2017",

month = mar,

day = "1",

doi = "10.1016/j.vlsi.2016.12.011",

language = "英语",

volume = "57",

pages = "132--146",

journal = "Integration",

issn = "0167-9260",

publisher = "Elsevier B.V.",

}

TY - JOUR

T1 - IPRM

T2 - IP core resource multiplexing of core wrapper design for reducing test application time in DVFS-based multicore SoCs

AU - Deng, Libao

AU - Zhang, Baoquan

AU - Wang, Sha

AU - Jin, Chengyu

PY - 2017/3/1

Y1 - 2017/3/1

N2 - A modify wrapper/test access mechanism(TAM) structure is described to explore the maximal potential capacity of TAM, named “IP cores resource multiplexing(IPRM)”, reducing test application time for DVFS-based multicore System-on-Chips(MSoCs). The IPRM core wrappers, different from standard wrappers, enable to isolated core wrapper resource again to store test data for embedded cores under test. An integer linear programming (ILP) formulation with IPRM wrapper is proposed to improve multi-site test. Experimental results of the ITC’02 SoC Benchmark show that IPRM core wrapper reduces the burdens on ATE effectively, and can reduce the test application time by 10–50%.

AB - A modify wrapper/test access mechanism(TAM) structure is described to explore the maximal potential capacity of TAM, named “IP cores resource multiplexing(IPRM)”, reducing test application time for DVFS-based multicore System-on-Chips(MSoCs). The IPRM core wrappers, different from standard wrappers, enable to isolated core wrapper resource again to store test data for embedded cores under test. An integer linear programming (ILP) formulation with IPRM wrapper is proposed to improve multi-site test. Experimental results of the ITC’02 SoC Benchmark show that IPRM core wrapper reduces the burdens on ATE effectively, and can reduce the test application time by 10–50%.

KW - DVFS

KW - Design for testability

KW - IP core resource multiplexing

KW - Multicore SoC testing

KW - Wrapper structure design

UR - https://www.scopus.com/pages/publications/85008177075

U2 - 10.1016/j.vlsi.2016.12.011

DO - 10.1016/j.vlsi.2016.12.011

M3 - 文章

AN - SCOPUS:85008177075

SN - 0167-9260

VL - 57

SP - 132

EP - 146

JO - Integration

JF - Integration

ER -

IPRM: IP core resource multiplexing of core wrapper design for reducing test application time in DVFS-based multicore SoCs

Abstract

Keywords

Access to Document

Other files and links

Fingerprint

Cite this