Skip to main navigation Skip to search Skip to main content

IP watermarking using incremental technology mapping at logic synthesis level

  • Aijiao Cui*
  • , Chip Hong Chang
  • , Sofiène Tahar
  • *Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

This paper proposes an adaptive watermarking technique by modulating some closed cones in an originally optimized logic network (master design) for technology mapping. The headroom of each disjoint closed cone is evaluated based on its slack and slack sustainability. The notion of slack sustainability in conjunction with an embedding threshold enables closed cones in the critical path to be qualified as watermark hosts if their slacks can be better preserved upon remapping. The watermark is embedded by remapping only qualified disjoint closed cones randomly selected and templates constrained by the signature. This parametric formulation provides a means to capitalize on the headroom of a design to increase the signature length or strengthen the watermark resilience. With the master design, the watermarked design can be authenticated as in nonoblivious media watermarking. Experimental results show that the design can be efficiently marked by our method with low overhead.

Original languageEnglish
Article number4603076
Pages (from-to)1565-1570
Number of pages6
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume27
Issue number9
DOIs
StatePublished - Sep 2008
Externally publishedYes

Keywords

  • Digital watermarking
  • Incremental technology mapping
  • Intellectual property (IP) protection (IPP)
  • Logic synthesis

Fingerprint

Dive into the research topics of 'IP watermarking using incremental technology mapping at logic synthesis level'. Together they form a unique fingerprint.

Cite this