Investigation of Elastic Fields within Through-silicon Vias using a Finite Element Model with Thermal Stresses and Joule Heating Present

Through-silicon vias, usually considered to a good candidate for vertical connections, lead to shorter length of connections and higher packaging densities. Here, a finite-element model is built to study the elastic performance of TSVs. The structure of a modeled TSV includes one dielectric layer (silicon dioxide) on the surface of the silicon chip and one BCB liner around the Cu via. Important factors such as thermal stresses, as well as Joule heating, are included in this model. First, the electric field is determined by solving a quasi-stationary equation of electrical conduction, which helps to find the effect of Joule heating. Then, a quasi-stationary equation on the temperature field is solved with Joule heating present to obtain the temperature distribution. Finally, the equations of mechanical equilibrium with thermal stresses present are solved to find the elastic displacements, which eventually lead to the elastic strains and stresses. Thus, the von Mises stress can be obtained and used for the evaluation of the elastic performance of TSVs. Simulation results show that the thermal stresses play an important role within TSVs. The maximums of Mises stress calculated at 35 °C and 45 °C are several times higher than that at the room temperature and the locations of these maximums are around the interfaces of the Cu via near the top and bottom boundaries. Joule heating is found to result in a maximum of the temperature at the center of the Cu via and lead to a further increase of the maximums of the Mises stress.