Influences on output distortion in voltage source inverter caused by power devices' parasitic capacitance

Insertion of dead time in space vector pulse width modulation (SVPWM) causes phase voltage and current distortion or even zero-current clamping phenomenon, degrading the control performance of ac induction motor. In addition, analysis of distortion becomes more complicated due to the existence of parasitic capacitance in power switching device of voltage source inverter (VSI). This paper tries to make clear that how the parasitic capacitance influences VSI's output independently. First, an equivalent circuit of VSI containing parasitic capacitance is constructed. On that basis, mathematical expression of phase voltage distortion is derived from Kirchhoff's voltage law, Kirchhoff's current law, and charge and discharge characteristics of capacitance. Moreover, through the division of multiple zero-crossing regions in one phase current period, the difficulty of obtaining specific phase voltage error expressions is overcome. Second, to figure out the effect of parasitic capacitance, it is theoretically discussed in detail that how parasitic capacitances of different values affect phase voltage, current distortion, and zero-current clamping phenomenon. At last, simulations and experiments are carried out in which VSI with different parasitic capacitances is constructed by paralleling additional capacitors and with phase voltage feedback methods, the theoretical analysis can be verified.