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Implementing listless minimum zerotree coding with FPGA

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A Listless Minimum Zerotree Coding algorithm (LMZC) on Field Programmable Gate Array (FPGA) is proposed to adopt a minimum zerotree of wavelet coefficients and a listless significance map coding with a new scanning order and new flag maps different from Listless Zerotree Coding (LZC) to reduce the memory requirement and increase the compression performance. Additionally, a pipelined hardware architecture is utilized, and characterized with higher speed and higher compression performance. Simulation results show that this scheme is feasible.

Original languageEnglish
Title of host publicationProceedings of the Second International Symposium on Instrumentation Science and Technology
EditorsT. Jiubin, W. Xianfang, T. Jiubin, W. Xianfang
Pages3/567-3/571
StatePublished - 2002
EventProceedings of the second International Symposium on Instrumentation Science and Technology - Jinan, China
Duration: 18 Aug 200222 Aug 2002

Publication series

NameProceedings of the Second International Symposium on Instrumentation Science and Technology
Volume3

Conference

ConferenceProceedings of the second International Symposium on Instrumentation Science and Technology
Country/TerritoryChina
CityJinan
Period18/08/0222/08/02

Keywords

  • FPGA
  • LMZC
  • LZC
  • Wavelet transform

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