@inproceedings{433de6041f12408abd15b07a684793d5,
title = "High Robust and Low Cost Soft Error Hardened Latch Design for Nanoscale CMOS Technology",
abstract = "We propose a high robust and low cost soft error hardened latch design applied to SMIC 65nm technology in this paper. With the method of SET filtering technique and inter-latching structure, the proposed latch can self-recover from SEUs and filter SETs. Simulation results have indicated that the proposed latch design possess high reliability and lowest PDP.",
author = "Li, \{Hong Chen\} and Xiao, \{Li Yi\} and Jie Li and Cao, \{Xue Bing\}",
note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 ; Conference date: 31-10-2018 Through 03-11-2018",
year = "2018",
month = dec,
day = "5",
doi = "10.1109/ICSICT.2018.8565650",
language = "英语",
series = "2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
editor = "Ting-Ao Tang and Fan Ye and Yu-Long Jiang",
booktitle = "2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings",
address = "美国",
}