High performance instruction set simulator using dynamic decode cache

The ISS (instruction set simulator) is an important tool for the SoC HW/SW co-design and co-verification. The simulator performance is a key factor for the overall design efficiency. Interpretive simulators have great flexibilities and are indispensable in the simulation of software involving self-modifying code, for example OS. This paper presents a high performance interpretive ISS, dynamic decode cache and several other optimization techniques are used to improve the simulation speed significantly. An ARM7 instruction set simulator is implemented for illustration, and the optimization techniques presented in this paper are also applicable for most other modern RISC architectures.