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High Density TSV-Free Interposer (TFI) packaging with submicron Cu Damascene RDLs for Integration of CPU/GPU and HBM

  • Masaya Kawano
  • , Chum Mei Wang
  • , Hong Yu Li
  • , Mian Zhi Ding
  • , Sharon Pei Siang Lim
  • , Teck Guan Lim
  • , Zi Hao Chen
  • , Fa Xing Che
  • Agency for Science, Technology and Research, Singapore

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

TSV-Free Interposer (TFI) packaging technology was developed for central/graphics processing unit (CPU/GPU) and stacked memory system-in-package (SiP) applications. TFI package is targeting to accommodate thick module as High Bandwidth Memory (HBM) and wide-bus interconnections between CPU/GPU and HBM in a package with cost-effective process. The redistribution layer structure was studied based on inter-chip connectivity between CPU/GPU and HBM as well as signal integrity and power integrity. This study demonstrated capability of TFI package in view of electrical performance, cost effectiveness and process challenges. The process challenges were overcome by co-design modeling and process optimizations.

Original languageEnglish
Title of host publicationProceedings - IEEE 68th Electronic Components and Technology Conference, ECTC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1885-1892
Number of pages8
ISBN (Print)9781538649985
DOIs
StatePublished - 7 Aug 2018
Externally publishedYes
Event68th IEEE Electronic Components and Technology Conference, ECTC 2018 - San Diego, United States
Duration: 29 May 20181 Jun 2018

Publication series

NameProceedings - Electronic Components and Technology Conference
Volume2018-May
ISSN (Print)0569-5503

Conference

Conference68th IEEE Electronic Components and Technology Conference, ECTC 2018
Country/TerritoryUnited States
CitySan Diego
Period29/05/181/06/18

Keywords

  • Cu damascene
  • FOWLP
  • Fan-out wafer-level packaging
  • RDL-first
  • TFI
  • TSV-free interposer

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