@inproceedings{6f9199516abe4f618345412d2cb84cde,
title = "Hardware transactional memory in multicore processors",
abstract = "The transactional memory in multicore processors has been a major area of research over past ten years. Many transactional memory architectures have been proposed to solve the synchronization problem of multicore processors. Hardware transactional memory is one of the critical methods to speedup communications between many cores. We give a review of the current Hardware Transactional Memory systems for Multicore processors. Hardware transactional memory systems are classified into the following two categories: whether to support unbounded transactional memory and whether to support transactions nesting. Finally, we discuss two active research challenges: the relationship between transactional memory and Input/Output operations and Instruction Set Architecture supporting.",
keywords = "Hardware, Multicore processor, Parallel programming, Synchronization, Transactional memory",
author = "Chen Fu and Hongwei Liu and Xiaoqun Wang and Dongxin Wen and Xiaozong Yang",
year = "2009",
doi = "10.1109/ICIECS.2009.5364966",
language = "英语",
isbn = "9781424449941",
series = "Proceedings - 2009 International Conference on Information Engineering and Computer Science, ICIECS 2009",
booktitle = "Proceedings - 2009 International Conference on Information Engineering and Computer Science, ICIECS 2009",
note = "2009 International Conference on Information Engineering and Computer Science, ICIECS 2009 ; Conference date: 19-12-2009 Through 20-12-2009",
}