Glitch minimization and low power FPGA routing algorithm

This paper describes a routing algorithm that limits the number of glitches in order to reduce dynamic power in FPGAs. The algorithm involves modifying cost function and aligning the arrival time of signals to the inputs of the lookup tables to filter out some glitches. During the same run time, experimental results demonstrate that the proposed method eliminates 23.4% of the glitches, reduces overall FPGA power by 5.4%, while, compared with the VPR, the critical-path delay only increases by 1% on average. Furthermore, the proposed method requires no additional hardware to reduce glitches.