FPGA On-Board computer design based on hierarchical fault tolerance

Safety is a crucial requirement of On-Board Computer (ODC) design of a satellite, especially for the new type ODC-takes FPGA as central processor. Upon that this paper proposes a plan ofFPGA ODC design and adds hierarchical fault tolerant concept to enhance the reliability of the ODC system. The fault tolerant architecture can be divided into three hierarchic ranks, containing single-CPU reconfiguration, component unit transfer and dual-CPU subrogation. One of the above fault manage mode will be chosen to deal with problems according to error situation in-orbit. In the worst cases, all three modes may be used. The last part of the paper gives the functional verification approach under development for the hierarchical fault tolerant ODC design.