Abstract
In the field of PMSM control, the current loop bandwidth represents the dynamic performance of the servo system. In this paper, based on the mathematical model, it is proved that the effective way to widen the current loop bandwidth under the condition of constant switching frequency is to reduce the computational delay of the current loop. In this paper, an improved piecewise and instant PWM duty cycle update method based on FPGA is proposed to reduce the complexity of the current loop computation when multi-sampling and multi-update are performed, which can effectively reduce the Computational delay, and the method can also improve the system DC bus voltage utilization. The feasibility of this method has been verified by experiments under different current conditions in permanent magnet synchronous motor.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of 2024 IEEE 7th International Electrical and Energy Conference, CIEEC 2024 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 2716-2721 |
| Number of pages | 6 |
| ISBN (Electronic) | 9798350359558 |
| DOIs | |
| State | Published - 2024 |
| Externally published | Yes |
| Event | 7th IEEE International Electrical and Energy Conference, CIEEC 2024 - Harbin, China Duration: 10 May 2024 → 12 May 2024 |
Publication series
| Name | Proceedings of 2024 IEEE 7th International Electrical and Energy Conference, CIEEC 2024 |
|---|
Conference
| Conference | 7th IEEE International Electrical and Energy Conference, CIEEC 2024 |
|---|---|
| Country/Territory | China |
| City | Harbin |
| Period | 10/05/24 → 12/05/24 |
UN SDGs
This output contributes to the following UN Sustainable Development Goals (SDGs)
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SDG 7 Affordable and Clean Energy
Keywords
- Computational Delay
- DC bus voltage utilization
- FPGA-based
- bandwidth improvement
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