FPGA implementation and verification of a pseudo-pipelined VLSI architecture of two elliptic curve scalar multiplications

Two elliptic curve scalar multiplications with independent input are used in some important elliptic curve cryptography algorithms. In order to reduce the execution time of these algorithms, a pseudo-pipelined VLSI architecture of two elliptic curve scalar multiplications over binary finite field GF (2 ^m) is proposed. The proposed architecture is implemented on FPGA board and verified by a systematic verification environment. A pseudo-pipelined word-serial finite field multiplier, with word size w, suitable for the two elliptic curve scalar multiplications is also developed. Implemented in hardware, this system performs two elliptic curve scalar multiplications in approximately 4-m/w-(m-1) clock cycles. Compared with other architectures proposed recently, it is shown that the computation time for elliptic curve scalar multiplication is the shortest by using our proposed VLSI architecture.