Flexible TAM-bus assignment method for solving SoC test scheduling problem

Test scheduling is an important issue in system-on-a-chip (SoC), and is widely recognized as a major bottleneck in SoC design. This NP-complete problem is equivalent to a 2-D bin-packing problem. In traditional method, each IP core is represented by a rectangle whose height equals to the test access mechanism (TAM) width and width equals to the test time. In this paper, we present a flexible TAM assignment method for solving SoC test scheduling problem. The main idea of the method is that the IP core is assigned to a group of test buses and the rectangle representing the IP core is divided into several ones in width. Meanwhile, cross-entropy (CE) method based on probability density function, and B^*-Tree structure based floor planning technique are used to solve the SoC test scheduling problem. The method was applied on ITC'02 benchmark test set, and experimental results show that compared with existing scheduling methods the proposed method can effectively reduce test time.