TY - GEN
T1 - Fine-grained analysis and design of ASIP instruction set for application of encryption
AU - Jinguo, Quan
AU - Ju, Jinbin
AU - Chen, Qian
AU - Zhang, Yan
PY - 2012
Y1 - 2012
N2 - Focusing on the defects of application-specific integrated processor (ASIP) design for encryption including complexity, long-term of development and lack of compatibility, in this paper we present an ASIP design method based on reconfigurable embedded RISC processor core, taking advantage of novel fine-grained code analysis technology. This relatively concise design process includes taking fine-grained analysis of target encryption code, extending instructions of the critical parts, and coupling the extended instructions as a co-processor in hardware structure with a general main-processor. As an instance, we take secure hash algorithm (SHA) as the target code, design and implement an ASIP in this process. The hardware verification and implementation result signifies that the designed processor has, at expense of relatively small chip area consumed, achieved obvious increase of performance for encryption.
AB - Focusing on the defects of application-specific integrated processor (ASIP) design for encryption including complexity, long-term of development and lack of compatibility, in this paper we present an ASIP design method based on reconfigurable embedded RISC processor core, taking advantage of novel fine-grained code analysis technology. This relatively concise design process includes taking fine-grained analysis of target encryption code, extending instructions of the critical parts, and coupling the extended instructions as a co-processor in hardware structure with a general main-processor. As an instance, we take secure hash algorithm (SHA) as the target code, design and implement an ASIP in this process. The hardware verification and implementation result signifies that the designed processor has, at expense of relatively small chip area consumed, achieved obvious increase of performance for encryption.
KW - ASIP
KW - co-processor
KW - encryption
KW - fine-grained analysis
KW - instruction extension
UR - https://www.scopus.com/pages/publications/84859915713
U2 - 10.1109/ICCNC.2012.6167398
DO - 10.1109/ICCNC.2012.6167398
M3 - 会议稿件
AN - SCOPUS:84859915713
SN - 9781467300094
T3 - 2012 International Conference on Computing, Networking and Communications, ICNC'12
SP - 144
EP - 148
BT - 2012 International Conference on Computing, Networking and Communications, ICNC'12
T2 - 2012 International Conference on Computing, Networking and Communications, ICNC'12
Y2 - 30 January 2012 through 2 February 2012
ER -