TY - GEN
T1 - Fine-grained analysis and design of ASIP instruction set for application of encryption
AU - Ju, Jinbin
AU - Jinguo, Quan
AU - Chen, Qian
AU - Zhang, Yan
PY - 2011
Y1 - 2011
N2 - Focusing on the defects of application-specific integrated processor (ASIP) design for encryption including complexity, long-term of development and lack of compatibility, in this paper we present an ASIP design method based on reconfigurable embedded RISC processor core, taking advantage of novel fine-grained code analysis technology. This relatively concise design process includes taking fine-grained analysis of target encryption code, extending instructions of the critical parts, and coupling the extended instructions as a co-processor in hardware structure with a general main-processor. As an instance, we take secure hash algorithm (SHA) as the target code, design and implement an ASIP in this process. The hardware verification and implementation result signifies that the designed processor has, at expense of relatively small chip area consumed, achieved obvious increase of performance for encryption.
AB - Focusing on the defects of application-specific integrated processor (ASIP) design for encryption including complexity, long-term of development and lack of compatibility, in this paper we present an ASIP design method based on reconfigurable embedded RISC processor core, taking advantage of novel fine-grained code analysis technology. This relatively concise design process includes taking fine-grained analysis of target encryption code, extending instructions of the critical parts, and coupling the extended instructions as a co-processor in hardware structure with a general main-processor. As an instance, we take secure hash algorithm (SHA) as the target code, design and implement an ASIP in this process. The hardware verification and implementation result signifies that the designed processor has, at expense of relatively small chip area consumed, achieved obvious increase of performance for encryption.
KW - ASIP
KW - co-processor
KW - encryption
KW - fine-grained analysis
KW - instruction extension
UR - https://www.scopus.com/pages/publications/84863163918
U2 - 10.1145/2103380.2103389
DO - 10.1145/2103380.2103389
M3 - 会议稿件
AN - SCOPUS:84863163918
SN - 9781450310871
T3 - Proceedings of the 2011 ACM Research in Applied Computation Symposium, RACS 2011
SP - 44
EP - 49
BT - Proceedings of the 2011 ACM Research in Applied Computation Symposium, RACS 2011
T2 - 2011 ACM Research in Applied Computation Symposium, RACS 2011
Y2 - 2 November 2011 through 5 November 2011
ER -