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FexMo: Enabling Fuse Execution Mode for Multi-task CGRAs

  • Harbin Institute of Technology
  • Beihang University

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Conventional CGRA multi-task resource allocation predominantly employs spatial partition, resulting in low temporal utilization of tiles. Our study reveals that fusing multiple tasks to share the whole CGRA can improve temporal utilization of tiles and introduce superior task throughput. However, this fuse execution mode brings two challenges: as nodes from multiple tasks' DFGs multiplex the same tiles, load misses from any task will block the execution of other tasks. Besides, existing CGRA mappers fail to constrain the scheduling when fuse mapping multiple tasks' DFGs collaboratively, which results in an imbalanced distribution of nodes along different modulo cycles. Both challenges hinder the full exploitation of the utilization and throughput advantages inherent to the fuse execution mode. To address these challenges, we propose FexMo, a novel framework supporting fused execution mode for multi-task CGRA. Architecturally, FexMo introduces checkpoints with clock-gating mechanisms. The contexts of any tasks that encounter load misses are checkpointed to preserve progress without blocking other tasks, and will be resumed for retrying every time at the same modulo cycle. During load misses, tasks execute NOPs on the clock-gated tiles, preventing errors and saving power. For fuse mapping, FexMo proposes inter-DFGs co-scheduling strategy, which evenly distributes nodes from all tasks across modulo cycles, maximizing temporal utilization of tiles and fully leveraging the throughput benefits of fuse execution mode. Extensive experiments demonstrate that FexMo achieves an average utilization gain of 36.9% and a 1.99 × throughput improvement over the conventional partition execution mode. FexMo-Mapper completes mapping within one minute, delivering solutions with 2.72 × higher quality than conventional mappers on average. Implementation using the ASAP7 PDK flow shows FexMo achieves 434MHz clock frequency with negligible area overhead. Despite inducing additional power consumption, FexMo maintains 1.22 × higher energy efficiency than the baseline on average.

Original languageEnglish
Title of host publicationMICRO 2025 - 58th IEEE/ACM International Symposium on Microarchitecture
PublisherIEEE Computer Society
Pages1236-1249
Number of pages14
ISBN (Electronic)9798400715730
DOIs
StatePublished - 17 Oct 2025
Event58th IEEE/ACM International Symposium on Microarchitecture , MICRO 2025 - Seoul, Korea, Republic of
Duration: 18 Oct 202522 Oct 2025

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
VolumePart of 213862
ISSN (Print)1072-4451

Conference

Conference58th IEEE/ACM International Symposium on Microarchitecture , MICRO 2025
Country/TerritoryKorea, Republic of
CitySeoul
Period18/10/2522/10/25

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

  1. SDG 7 - Affordable and Clean Energy
    SDG 7 Affordable and Clean Energy

Keywords

  • Architectural support
  • CGRA
  • CGRA mapper
  • Fuse execution mode
  • Multi-task

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