Exploration of a reconfigurable 2D mesh network-on-chip architecture and a topology reconfiguration algorithm

Zi Xu Wu; Jin Xiang Wang; Ji Yuan Zhang; Xiao Yu Wang; Fang Fa Fu

doi:10.1109/ICSICT.2012.6466732

Exploration of a reconfigurable 2D mesh network-on-chip architecture and a topology reconfiguration algorithm

Zi Xu Wu^*
, Jin Xiang Wang
, Ji Yuan Zhang
, Xiao Yu Wang
, Fang Fa Fu

^*Corresponding author for this work

School of Astronautics

Harbin Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Scopus citations

Abstract

A novel reconfigurable 2D mesh Network-on-Chip (NoC) architecture (REmesh) and a topology reconfiguration algorithm (TRARE) are proposed in this paper. Compared with a conventional 2D mesh, REmesh, which employs a few more routers and multiplexers, can be easily reconfigured to restore a 2D mesh topology to tolerant core faults in NoCs. Based on REmesh, TRARE repeatedly categorizes routers, connects cores with routers, and eventually finds out a reconfiguration solution. Simulation results show that in the topologies which sizes do not exceed 7×8, more than 90% successful reconfiguration rate can be guaranteed when less than 9% of the total cores are faulty. Simulation also suggests that when the number of faulty cores reaches the number of redundant cores, more redundancy should be added to ensure high successful reconfiguration rate.

Original language	English
Title of host publication	ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
DOIs	https://doi.org/10.1109/ICSICT.2012.6466732
State	Published - 2012
Event	2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012 - Xi'an, China Duration: 29 Oct 2012 → 1 Nov 2012

Publication series

Name	ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Conference

Conference	2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012
Country/Territory	China
City	Xi'an
Period	29/10/12 → 1/11/12

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10.1109/ICSICT.2012.6466732

Cite this

Wu, Z. X., Wang, J. X., Zhang, J. Y., Wang, X. Y., & Fu, F. F. (2012). Exploration of a reconfigurable 2D mesh network-on-chip architecture and a topology reconfiguration algorithm. In ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings Article 6466732 (ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings). https://doi.org/10.1109/ICSICT.2012.6466732

Wu, Zi Xu ; Wang, Jin Xiang ; Zhang, Ji Yuan et al. / Exploration of a reconfigurable 2D mesh network-on-chip architecture and a topology reconfiguration algorithm. ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2012. (ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings).

@inproceedings{0012de8c48334bcbb4f2e3741064bb08,

title = "Exploration of a reconfigurable 2D mesh network-on-chip architecture and a topology reconfiguration algorithm",

abstract = "A novel reconfigurable 2D mesh Network-on-Chip (NoC) architecture (REmesh) and a topology reconfiguration algorithm (TRARE) are proposed in this paper. Compared with a conventional 2D mesh, REmesh, which employs a few more routers and multiplexers, can be easily reconfigured to restore a 2D mesh topology to tolerant core faults in NoCs. Based on REmesh, TRARE repeatedly categorizes routers, connects cores with routers, and eventually finds out a reconfiguration solution. Simulation results show that in the topologies which sizes do not exceed 7×8, more than 90\% successful reconfiguration rate can be guaranteed when less than 9\% of the total cores are faulty. Simulation also suggests that when the number of faulty cores reaches the number of redundant cores, more redundancy should be added to ensure high successful reconfiguration rate.",

author = "Wu, \{Zi Xu\} and Wang, \{Jin Xiang\} and Zhang, \{Ji Yuan\} and Wang, \{Xiao Yu\} and Fu, \{Fang Fa\}",

year = "2012",

doi = "10.1109/ICSICT.2012.6466732",

language = "英语",

isbn = "9781467324724",

series = "ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings",

booktitle = "ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings",

note = "2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012 ; Conference date: 29-10-2012 Through 01-11-2012",

}

Wu, ZX, Wang, JX, Zhang, JY, Wang, XY & Fu, FF 2012, Exploration of a reconfigurable 2D mesh network-on-chip architecture and a topology reconfiguration algorithm. in ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings., 6466732, ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012, Xi'an, China, 29/10/12. https://doi.org/10.1109/ICSICT.2012.6466732

Exploration of a reconfigurable 2D mesh network-on-chip architecture and a topology reconfiguration algorithm. / Wu, Zi Xu; Wang, Jin Xiang; Zhang, Ji Yuan et al.
ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2012. 6466732 (ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Exploration of a reconfigurable 2D mesh network-on-chip architecture and a topology reconfiguration algorithm

AU - Wu, Zi Xu

AU - Wang, Jin Xiang

AU - Zhang, Ji Yuan

AU - Wang, Xiao Yu

AU - Fu, Fang Fa

PY - 2012

Y1 - 2012

N2 - A novel reconfigurable 2D mesh Network-on-Chip (NoC) architecture (REmesh) and a topology reconfiguration algorithm (TRARE) are proposed in this paper. Compared with a conventional 2D mesh, REmesh, which employs a few more routers and multiplexers, can be easily reconfigured to restore a 2D mesh topology to tolerant core faults in NoCs. Based on REmesh, TRARE repeatedly categorizes routers, connects cores with routers, and eventually finds out a reconfiguration solution. Simulation results show that in the topologies which sizes do not exceed 7×8, more than 90% successful reconfiguration rate can be guaranteed when less than 9% of the total cores are faulty. Simulation also suggests that when the number of faulty cores reaches the number of redundant cores, more redundancy should be added to ensure high successful reconfiguration rate.

AB - A novel reconfigurable 2D mesh Network-on-Chip (NoC) architecture (REmesh) and a topology reconfiguration algorithm (TRARE) are proposed in this paper. Compared with a conventional 2D mesh, REmesh, which employs a few more routers and multiplexers, can be easily reconfigured to restore a 2D mesh topology to tolerant core faults in NoCs. Based on REmesh, TRARE repeatedly categorizes routers, connects cores with routers, and eventually finds out a reconfiguration solution. Simulation results show that in the topologies which sizes do not exceed 7×8, more than 90% successful reconfiguration rate can be guaranteed when less than 9% of the total cores are faulty. Simulation also suggests that when the number of faulty cores reaches the number of redundant cores, more redundancy should be added to ensure high successful reconfiguration rate.

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Wu ZX, Wang JX, Zhang JY, Wang XY, Fu FF. Exploration of a reconfigurable 2D mesh network-on-chip architecture and a topology reconfiguration algorithm. In ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2012. 6466732. (ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings). doi: 10.1109/ICSICT.2012.6466732

Exploration of a reconfigurable 2D mesh network-on-chip architecture and a topology reconfiguration algorithm

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