TY - GEN
T1 - Evolutionary design of relatively large combinational circuits with an extended stepwise dimension reduction
AU - Li, Zhifang
AU - Luo, Wenjian
AU - Yue, Lihua
AU - Wang, Xufa
PY - 2009
Y1 - 2009
N2 - In this paper, an eXtended Stepwise Dimension Reduction approach (XSDR) to evolutionary design of relatively large combinational logic circuits is proposed. In our previous work, a Stepwise Dimension Reduction approach (SDR) is introduced. The SDR divides a circuit into several layers. The layers are evolved one after another. However, some layers are difficult to be evolved. The XSDR improves the SDR by decomposing the original truth table of a layer to two truth tables. The new truth tables after decomposing are easy to be evolved. The proposed method has been tested with multipliers and the circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library. The experimental results demonstrate that the XSDR extensively improves the performance of the SDR in terms of the number of fitness evaluations and the computational time.
AB - In this paper, an eXtended Stepwise Dimension Reduction approach (XSDR) to evolutionary design of relatively large combinational logic circuits is proposed. In our previous work, a Stepwise Dimension Reduction approach (SDR) is introduced. The SDR divides a circuit into several layers. The layers are evolved one after another. However, some layers are difficult to be evolved. The XSDR improves the SDR by decomposing the original truth table of a layer to two truth tables. The new truth tables after decomposing are easy to be evolved. The proposed method has been tested with multipliers and the circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library. The experimental results demonstrate that the XSDR extensively improves the performance of the SDR in terms of the number of fitness evaluations and the computational time.
KW - Combinational logic circuit
KW - Evolutionary algorithm
KW - Evolvable hardware
UR - https://www.scopus.com/pages/publications/77950591936
U2 - 10.1109/DASC.2009.48
DO - 10.1109/DASC.2009.48
M3 - 会议稿件
AN - SCOPUS:77950591936
SN - 9780769539294
T3 - 8th IEEE International Symposium on Dependable, Autonomic and Secure Computing, DASC 2009
SP - 119
EP - 124
BT - 8th IEEE International Symposium on Dependable, Autonomic and Secure Computing, DASC 2009
T2 - 8th IEEE International Symposium on Dependable, Autonomic and Secure Computing, DASC 2009
Y2 - 12 December 2009 through 14 December 2009
ER -