Evaluation of the μController networks communication for EtherCAT process data interface

According to the EtherCAT process data interface networks system designs, we determined that the Synchronous and Asynchronous μController scheme evaluations based on the FPGA state machine algorithm. The present study focuses on the Schematic of μController interconnection between FPGA and ESC based on the VHDL state machine algorithm, which includes state machine programs. In addition, the performance of the Synchronous and Asynchronous μController was verified through numerical simulations. Furthermore, we found the simulations gave further evidence that the 16 bits synchronous and Asynchronous μController signals can satisfy the two write access and a read access requirements for the EtherCAT networks communication. Finally, the results include the positive and negative aspects of the Synchronous and Asynchronous μController networks communication, and the comparison the results of the Synchronous, Asynchronous and SPI communication evaluations done by the researchers.