Ethercat slave controller via an asynchronous 16 bit μController algorithm based on FPGA

A novel 16 bit Asynchronous μController based on FPGA state machine algorithm for the EtherCAT Slaved during write and read access is described in this paper. The present study focuses on the Schematic of μController interconnection between FPGA and ESC based on the VHDL state machine algorithm, which includes fifteen states. In addition, the performance of the Asynchronous μController was verified through numerical simulations. Finally, we found the simulations give further evidence that the 16 bits Asynchronous μController signals can satisfy two write access and a read accesses requirements for the EtherCAT Slave Controller.