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Error Detection and Correction Codes for Memories with Enhanced Detection Abilities

  • Harbin Institute of Technology

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Recent memories in different processors suffer from increasing threats of errors. Error correction and detection codes with higher detection abilities are required. This work presents the design and implement of error control abilities of codes in different data lengths, realizing burst error correction abilities from 1 bit to 4 bits, detection abilities of 3-bit random errors and detection abilities of over 5 bits burst errors. Lower hardware overhead is realized for error detection. The proposed codes can be adopted to improve reliability of memories when increasing bits of burst errors and random errors need correcting and recovering.

Original languageEnglish
Title of host publication2024 IEEE 7th International Conference on Electronics and Communication Engineering, ICECE 2024
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages165-168
Number of pages4
ISBN (Electronic)9798331517755
DOIs
StatePublished - 2024
Event7th IEEE International Conference on Electronics and Communication Engineering, ICECE 2024 - Xi'an, China
Duration: 6 Oct 20248 Oct 2024

Publication series

Name2024 IEEE 7th International Conference on Electronics and Communication Engineering, ICECE 2024

Conference

Conference7th IEEE International Conference on Electronics and Communication Engineering, ICECE 2024
Country/TerritoryChina
CityXi'an
Period6/10/248/10/24

Keywords

  • Error control codes
  • burst error correction
  • error detection
  • lower overhead

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