Efficient two-dimensional error codes for multiple bit upsets mitigation in memory

As technology scales, more and more memory cells can be placed in a die. Multiple bit upsets (MBUs) induced by a single event in adjacent memory cells gets significantly increased. This paper proposes the efficient two-dimensional error codes to mitigate radiation-induced MBUs in memory. This scheme can correct MBUs with any possible width and assure the reliability of memory with very low cost overhead. Firstly, each word is transformed to a matrix form. Then, low complexity multibit error detection codes are applied in each row for error detection while parity codes are applied in each column for error correction. Furthermore, the layout architecture of two-dimensional error codes is used to mitigate MBUs in the redundancy bits. The proposed scheme has been implemented in Verilog and validated through a wide set of simulations. The experiment results reveal that the proposed method has a superior protection level. Compared with the existing multibit error correction codes, it has lower encoding and decoding overheads, even for Hamming codes.