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Effects of mask patterns optimization and silicon surface preparation for anisotropic silicon etching

  • B. K. Tan*
  • , M. Huang
  • , J. Wei
  • *Corresponding author for this work
  • Agency for Science, Technology and Research, Singapore
  • Micron Semiconductor Asia Pte Ltd.

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Anisotropic wet etching is a commonly used technique to selectively make trenches and holes to form silicon structures required in the fabrication of micro sensors, actuators and many silicon based MEMS devices. The feature size and pattern on the mask and the mask alignment to crystal orientation are important to determine the final etch pattern with crystalline dependent anisotropic etchant like KOH. Depending on the silicon wafer type, taking (100) silicon as an example, etching can only occur along the plane that is generally 54.74° to the wafer's surface. From a film or glass mask, the patterns are first transferred from the mask onto the photoresist spin coated on the SiO 2 surface that is used as an oxide hard mask. With a CVD approach, the desired pattern on the oxide mask are then dry etch away under protection of the photoresist to expose the silicon surface for wet etching. Typically the etch patterns are designed to the full feature size and the shape of the via and trench required. However, with this method, the agitation of gas form during wet etch weakens the edge of the oxide mask causing break off undercut resulting in an enlargement of etch size and poor surface finishing. In this paper the effects of changing the mask feature shape were evaluated. The optimization of mask patterning methodology has successfully improved both hard mask integrity and achieved much better etch uniformity.

Original languageEnglish
Title of host publicationProceedings of 7th Electronics Packaging Technology Conference, EPTC 2005
Pages590-593
Number of pages4
StatePublished - 2005
Externally publishedYes
Event7th Electronics Packaging Technology Conference, EPTC 2005 - Singapore, Singapore
Duration: 7 Dec 20059 Dec 2005

Publication series

NameProceedings of 7th Electronics Packaging Technology Conference, EPTC 2005
Volume2

Conference

Conference7th Electronics Packaging Technology Conference, EPTC 2005
Country/TerritorySingapore
CitySingapore
Period7/12/059/12/05

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