Effect of thermal cycling on the strain and stress distribution of TSVs and solder bumps in stacked package structure

Aerospace exploration requires electronic devices to withstand the test of extreme environments, and it is of great significance to study the reliability of packaged devices at extreme temperatures. In this paper, the Anand model is used to describe the mechanical constitutive behavior of Sn-3.0Ag-0.5Cu (SAC305) solder and through-silicon via (TSV) in a 3D package structure, and the thermal cycling behavior of controlled collapse chip connection (C4) bumps and TSV arrays under thermal cycling from -100 to 120 °C is analyzed. The thermal fatigue life of C4 bumps and TSVs was evaluated according to the modified Coffin-Manson model. The results show that the maximum stress is 50.57 MPa at the contact interface between the C4 bump and the chip, which is caused by local thermal mismatch. The maximum equivalent plastic strain of the key bump is 1.6 × 10⁻² and its fatigue life under extreme temperature thermal cycling conditions is about 1366 cycles. The maximum equivalent plastic strain of the TSV array is 2.8 × 10⁻², located at the corner of the peripheral TSV, which is the most dangerous position in the TSV array, and its thermal fatigue life is about 1.9 × 10⁶ cycles.