Dynamic bottleneck analysis for semiconductor wafer fabrication system based on growing and pruning neural networks

Bottleneck is the key factor to semiconductor wafer fabrication system (SWFS), which seriously influences the level of work-in-process, cycle time, time-delivery rate, etc. Efficient analysis for the bottleneck of SWFS can promote various performances. In modern SWFS, present analysis methods usually regard bottleneck device as static bottleneck without taking bottleneck shifting into consideration in the uncertain environment, which leads to scheduling algorithm that always treat the bottleneck device as the core lack of flexibility and real-time performance. Therefore, dynamic bottleneck analysis method for the SWFS based on growing and pruning neural networks (GPNN) was adopted in this study to acquire the dynamic bottleneck characteristic. Firstly, in this paper, the way of composite definition is used to calculate comprehensive bottleneck degree of the devices form the perspectives of relative production load, utilization rate and length of the buffer queue to indicate bottleneck based on bottleneck identification mechanism; Secondly, establish the model of growing and pruning neural networks to predict the future bottleneck and adjust the network structure in view of closed-loop control. Thirdly, in order to analyze the key factors relative to bottleneck devices and the dynamic bottleneck characteristic quantitatively, the single factor test method was applied in this paper. Lastly, the experiments show that this dynamic bottleneck analysis method is testified the feasibility and availability.