DSTN sleep transistor sizing with a new approach to estimate the maximum instantaneous current

Yu Sun; Li Yi Xiao; Cong Shi

doi:10.1109/ISCAS.2010.5537752

DSTN sleep transistor sizing with a new approach to estimate the maximum instantaneous current

Yu Sun^*
, Li Yi Xiao
, Cong Shi

^*Corresponding author for this work

School of Astronautics

Harbin Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Power gating is one of most effective ways to suppress the leakage power in CMOS digital circuits. In this paper, we propose a new method to estimate the maximum instantaneous current (MIC), and derive an analytical model for the MIC of the clusters in distributed sleep transistor network (DSTN) power-gated circuits. Based on this MIC estimation model, we perform ST sizing in DSTN power-gated circuits. Experimental results show that we have achieved higher precision and less runtime.

Original language	English
Title of host publication	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
Subtitle of host publication	Nano-Bio Circuit Fabrics and Systems
Publisher	IEEE Computer Society
Pages	3717-3720
Number of pages	4
ISBN (Print)	9781424453085
DOIs	https://doi.org/10.1109/ISCAS.2010.5537752
State	Published - 2010
Event	2010 IEEE International Symposium on Circuits and Systems, ISCAS 2010 - Paris, France Duration: 30 May 2010 → 2 Jun 2010

Publication series

Name	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Conference

Conference	2010 IEEE International Symposium on Circuits and Systems, ISCAS 2010
Country/Territory	France
City	Paris
Period	30/05/10 → 2/06/10

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10.1109/ISCAS.2010.5537752

Cite this

Sun, Y., Xiao, L. Y., & Shi, C. (2010). DSTN sleep transistor sizing with a new approach to estimate the maximum instantaneous current. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (pp. 3717-3720). Article 5537752 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). IEEE Computer Society. https://doi.org/10.1109/ISCAS.2010.5537752

Sun, Yu ; Xiao, Li Yi ; Shi, Cong. / DSTN sleep transistor sizing with a new approach to estimate the maximum instantaneous current. ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. IEEE Computer Society, 2010. pp. 3717-3720 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

@inproceedings{3e131fc89b7d437dac8d01cbb208c9be,

title = "DSTN sleep transistor sizing with a new approach to estimate the maximum instantaneous current",

abstract = "Power gating is one of most effective ways to suppress the leakage power in CMOS digital circuits. In this paper, we propose a new method to estimate the maximum instantaneous current (MIC), and derive an analytical model for the MIC of the clusters in distributed sleep transistor network (DSTN) power-gated circuits. Based on this MIC estimation model, we perform ST sizing in DSTN power-gated circuits. Experimental results show that we have achieved higher precision and less runtime.",

author = "Yu Sun and Xiao, \{Li Yi\} and Cong Shi",

year = "2010",

doi = "10.1109/ISCAS.2010.5537752",

language = "英语",

isbn = "9781424453085",

series = "ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems",

publisher = "IEEE Computer Society",

pages = "3717--3720",

booktitle = "ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems",

address = "美国",

note = "2010 IEEE International Symposium on Circuits and Systems, ISCAS 2010 ; Conference date: 30-05-2010 Through 02-06-2010",

}

Sun, Y, Xiao, LY & Shi, C 2010, DSTN sleep transistor sizing with a new approach to estimate the maximum instantaneous current. in ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems., 5537752, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, IEEE Computer Society, pp. 3717-3720, 2010 IEEE International Symposium on Circuits and Systems, ISCAS 2010, Paris, France, 30/05/10. https://doi.org/10.1109/ISCAS.2010.5537752

DSTN sleep transistor sizing with a new approach to estimate the maximum instantaneous current. / Sun, Yu; Xiao, Li Yi; Shi, Cong.
ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. IEEE Computer Society, 2010. p. 3717-3720 5537752 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - DSTN sleep transistor sizing with a new approach to estimate the maximum instantaneous current

AU - Sun, Yu

AU - Xiao, Li Yi

AU - Shi, Cong

PY - 2010

Y1 - 2010

N2 - Power gating is one of most effective ways to suppress the leakage power in CMOS digital circuits. In this paper, we propose a new method to estimate the maximum instantaneous current (MIC), and derive an analytical model for the MIC of the clusters in distributed sleep transistor network (DSTN) power-gated circuits. Based on this MIC estimation model, we perform ST sizing in DSTN power-gated circuits. Experimental results show that we have achieved higher precision and less runtime.

AB - Power gating is one of most effective ways to suppress the leakage power in CMOS digital circuits. In this paper, we propose a new method to estimate the maximum instantaneous current (MIC), and derive an analytical model for the MIC of the clusters in distributed sleep transistor network (DSTN) power-gated circuits. Based on this MIC estimation model, we perform ST sizing in DSTN power-gated circuits. Experimental results show that we have achieved higher precision and less runtime.

UR - https://www.scopus.com/pages/publications/77955998339

U2 - 10.1109/ISCAS.2010.5537752

DO - 10.1109/ISCAS.2010.5537752

M3 - 会议稿件

AN - SCOPUS:77955998339

SN - 9781424453085

T3 - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

SP - 3717

EP - 3720

BT - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems

PB - IEEE Computer Society

T2 - 2010 IEEE International Symposium on Circuits and Systems, ISCAS 2010

Y2 - 30 May 2010 through 2 June 2010

ER -

Sun Y, Xiao LY, Shi C. DSTN sleep transistor sizing with a new approach to estimate the maximum instantaneous current. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. IEEE Computer Society. 2010. p. 3717-3720. 5537752. (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). doi: 10.1109/ISCAS.2010.5537752

DSTN sleep transistor sizing with a new approach to estimate the maximum instantaneous current

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