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DSP implementation of deblocking filter for AVS

  • Yang Zhigang*
  • , Gao Wen
  • , Liu Yan
  • , Zhao Debin
  • *Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The in-loop deblocking filter contains highly adaptive processing on both sample level and block edge level, which inevitably appears in the loop kernel of the algorithm. Therefore it is a challenge for parallel processing on a digital signal processor (DSP) platform. In this paper, pipelined DSP solutions to the in-loop deblocking filter in AVS1-P2 are presented. First, the whole filter process is divided into six sub-processes, so that the global filter structure can be improved to achieve regular processing flow. Then software pipelines are designed for these sub-processes, with elaborately allocating functional units and carefully choosing enhanced assembly instructions based on the DSP platform. The simulated results show that this efficient implementation can easily support real-time filter processing for high resolution videos.

Original languageEnglish
Title of host publication2007 IEEE International Conference on Image Processing, ICIP 2007 Proceedings
PagesVI205-VI208
DOIs
StatePublished - 2006
Event14th IEEE International Conference on Image Processing, ICIP 2007 - San Antonio, TX, United States
Duration: 16 Sep 200719 Sep 2007

Publication series

NameProceedings - International Conference on Image Processing, ICIP
Volume6
ISSN (Print)1522-4880

Conference

Conference14th IEEE International Conference on Image Processing, ICIP 2007
Country/TerritoryUnited States
CitySan Antonio, TX
Period16/09/0719/09/07

Keywords

  • AVS
  • Deblocking filter
  • Digital signal processors
  • Pipelines

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