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DPSK signal carrier synchronization module implemented on the FPGA

  • School of Electronics and Information Engineering, Harbin Institute of Technology
  • Science and Technology on Communication Networks Laboratory
  • Harbin Engineering University

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper proposes a method to implement the modified square loop digitally on the FPGA to solve the problem, that the divide circuit in the traditional square loop is difficult to achieve. The modified square loop has a similar structure to the traditional square loop. The method of modified square loop is to multiply quadrature output together to replace the divide circuit. In this paper, a specific method is given to digitize the square loop. The output carrier signal and the frequency difference will be analyzed in the condition of different initial frequency offset, parameters of the loop filter and input SNR.

Original languageEnglish
Title of host publicationProceedings - 2016 6th International Conference on Instrumentation and Measurement, Computer, Communication and Control, IMCCC 2016
EditorsJunbao Li
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1015-1020
Number of pages6
ISBN (Electronic)9781509011957
DOIs
StatePublished - 5 Dec 2016
Externally publishedYes
Event6th International Conference on Instrumentation and Measurement, Computer, Communication and Control, IMCCC 2016 - Harbin, Heilongjiang, China
Duration: 21 Jul 201623 Jul 2016

Publication series

NameProceedings - 2016 6th International Conference on Instrumentation and Measurement, Computer, Communication and Control, IMCCC 2016

Conference

Conference6th International Conference on Instrumentation and Measurement, Computer, Communication and Control, IMCCC 2016
Country/TerritoryChina
CityHarbin, Heilongjiang
Period21/07/1623/07/16

Keywords

  • Carrier synchronization
  • Digital phase-locked loop
  • FPGA
  • Square loop

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