Distinctive inverter delay model applied to variation delay analysis

This paper proposes an inverter gate delay model that is comprehensive for inverter gate delay analysis considering substrate coupling. The proposed model transforms the CMOS inverter delay to resistor and capacitance (RC) delay, and then computes the RC network delay under the process variation considering substrate coupling effect. The delay model analysis uses stochastic collocation methods combined with a polynomial chaos, which considers within-die process variation and substrate coupling effect. Experimental results are based on numerical calculation method. Simulation results show that the method's proportional error is less than 2% compared to HSPICE simulation.