Abstract
In order to improve dynamic performance to load variation of power factor correction (PFC) output voltage, a digital PFC algorithm with fast dynamic response was proposed through analyzing voltage loop influence on input and output harmonics. The proposed algorithm improves dynamic response by increasing voltage loop bandwidth, and uses vector rotation scheme to generate compensating harmonic signal which counteracts second order harmonic resulted from increased voltage loop bandwidth. Without adding auxiliary circuit, the fast dynamic response digital algorithm is programmed with graphical approach which corresponds to control chip. Experimental results verify that the system has fast dynamic response when the load power varies in a large-scale, the input current total harmonic distortion (THD) is lower than 10% and power factor reaches 0.99.
| Original language | English |
|---|---|
| Pages (from-to) | 10-15 |
| Number of pages | 6 |
| Journal | Zhongguo Dianji Gongcheng Xuebao/Proceedings of the Chinese Society of Electrical Engineering |
| Volume | 29 |
| Issue number | 12 |
| State | Published - 25 Apr 2009 |
| Externally published | Yes |
Keywords
- Digital power factor correction
- Fast dynamic response
- Vector rotation
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