Development of a readout system for the tentative pixel detectors at HIRFL

This paper presents a common readout system for the development of the pixel detectors at the HIRFL. The readout system consists of the front-end cards (FEC) and the common data acquisition unit (CDAU). The FEC reads data from the customized detector boards and sends it to the CDAU through the high-speed optical fiber link. To reduce the risk of radiation-induced failures, the Flash-based Microsemi Smartfusion2 FPGA SOC has been chosen as the main FPGA on the FEC. The CDAU receives data from the FECs, processes the data and ships the data to the data computer through the PCIe interface. This paper will discuss the design, implementation and first test results of this readout system.