Designing a synchronous error correction pipeline for dealing with SEU

The introduction of the full paper points out that SEU (single event upset) is one of the important causes of fault or even failure of satellite-borne computer. Using the Longtium-FT2 microprocessor developed by NWPU as an example, we explain our design in sections 1, 2 and 3. Section 1 analyzes Ref. 6 and points out that the direct error correction pipeline induces inherently significant penalty on the microprocessor's performance. Section 2 designs the synchronous error correction pipeline's architecture, whose block diagram is shown in Fig. 2. Its core is that the error correction structure is divided into the detection part and the correction part; when a correctable error occurs, the corrected data are written into the register file, and then the pipeline is restarted. Section 3 presents Figs. 3 through 6 to analyze respectively the performances of the pipeline when its instructions: (1) are normally executed, (2) generate a trap, (3) produce a correctable error, (4) produce an uncorrectable error. Section 4 implements the Longtium-FT2 microprocessor, whose chip is shown in Fig. 7, and verifies it with some experiments; the experimental results show preliminarily that the Longtium-FT2 microprocessor we designed is reliable and can tolerate SEU up to 30 Krads (Si) for the case of the microprocessor's being implemented in commercial fabrication processes.