Abstract
A high-speed memory system is proposed for reconfigurable codec processor to access high data throughput rates in video codec applications. The full duplex frame buffer and DMA are included in this new memory system. The frame buffer contains two memories with the size of 4 kbyte and is divided into 16 banks. Two-dimensional address coding is introduced as well as data arrangement switch for fast sequential data access by codec algorithm. The simulation result shows that the memory system can meet high performance requirement for reconfigurable processor ReMAP-2 in high-definition video codec application.
| Original language | English |
|---|---|
| Pages (from-to) | 150-156 |
| Number of pages | 7 |
| Journal | Shenzhen Daxue Xuebao (Ligong Ban)/Journal of Shenzhen University Science and Engineering |
| Volume | 30 |
| Issue number | 2 |
| DOIs | |
| State | Published - Mar 2013 |
| Externally published | Yes |
Keywords
- Digital signal processing
- Discrete cosine transform
- Integrated circuit technology
- Memory
- Multimedia processing
- Processor
- Reconfigurable
- Video codec
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