Design of high-performance fourth-order single-loop sigma-delta modulator for inertial sensor

In this paper, a design of high-performance fourth-order single-loop modulator applied in inertial sensor is described. This design employs the structure of feed-forward summation to reduce the output of the integrators and make the system more stable. Meanwhile, the modulator uses local feedback for zero optimization to improve the shaping capacity of the modulator noise within the signal bandwidth. In this sigma delta modulator, over-sampling rate is 256 and the signal bandwidth is 500 Hz, while sampling clock frequency is 250 KHz. By the Simulink simulation of MATLAB, the SNR is 145.6 dB and the Effective Number of Bits is 23.89. Transistorlevel circuit can be realized by single-end switched-capacitor circuits. A operational amplifier in the modulator, a dynamic comparator and a clock generation circuit are designed. The modulator has been implemented in CMOS 0.6 um process and simulated in Cadence. Transistor-level circuit simulation result shows that SNR is 126.6 dB, the Effective Number of Bits is 20.7, and nonlinearity of the single-end circuit generates circuit harmonic.