Design of digital standard cell based on silicon tunnel field-effect transistor

Hang Su; Yiwen Wang; Jipan Huang; Yufei Han; Mingjiang Wang

doi:10.1109/ICASID.2015.7405663

Design of digital standard cell based on silicon tunnel field-effect transistor

Hang Su^*
, Yiwen Wang
, Jipan Huang
, Yufei Han
, Mingjiang Wang

^*Corresponding author for this work

Harbin Institute of Technology Shenzhen
Peking University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Tunnel FETs was selected as the carrier of digital standard cell design since its excellent characteristics in low power consumption. This experiment contains the principle and characteristic of the Tunnel FETs, and specific standard cell circuit design based on the given model. In this design, we completed several combinational logic cells and sequential logic cells, and did the simulation. From the result of the simulation, we find that TFET devices' speed is slower than MOS device, but the power consumption can reduce to less than 10% of the same size MOS device. Also, by comparing with the MOS devices, we made the corresponding layout design and DRC rule changes, and as one of the results, the area of TFET device is at least 30% larger the MOS device.

Original language	English
Title of host publication	Proceedings of 2015 IEEE 9th International Conference on Anti-Counterfeiting, Security and Identification, ASID 2015
Publisher	IEEE Computer Society
Pages	66-70
Number of pages	5
ISBN (Electronic)	9781467371391
DOIs	https://doi.org/10.1109/ICASID.2015.7405663
State	Published - 11 Feb 2016
Externally published	Yes
Event	9th IEEE International Conference on Anti-Counterfeiting, Security and Identification, ASID 2015 - Xiamen, China Duration: 25 Sep 2015 → 27 Sep 2015

Publication series

Name	Proceedings of the International Conference on Anti-Counterfeiting, Security and Identification, ASID
Volume	2016-February
ISSN (Print)	2163-5048
ISSN (Electronic)	2163-5056

Conference

Conference	9th IEEE International Conference on Anti-Counterfeiting, Security and Identification, ASID 2015
Country/Territory	China
City	Xiamen
Period	25/09/15 → 27/09/15

Keywords

TFET
layout
powever consumpution
standard cell

Access to Document

10.1109/ICASID.2015.7405663

Cite this

Su, H., Wang, Y., Huang, J., Han, Y., & Wang, M. (2016). Design of digital standard cell based on silicon tunnel field-effect transistor. In Proceedings of 2015 IEEE 9th International Conference on Anti-Counterfeiting, Security and Identification, ASID 2015 (pp. 66-70). Article 7405663 (Proceedings of the International Conference on Anti-Counterfeiting, Security and Identification, ASID; Vol. 2016-February). IEEE Computer Society. https://doi.org/10.1109/ICASID.2015.7405663

Su, Hang ; Wang, Yiwen ; Huang, Jipan et al. / Design of digital standard cell based on silicon tunnel field-effect transistor. Proceedings of 2015 IEEE 9th International Conference on Anti-Counterfeiting, Security and Identification, ASID 2015. IEEE Computer Society, 2016. pp. 66-70 (Proceedings of the International Conference on Anti-Counterfeiting, Security and Identification, ASID).

@inproceedings{cb6a6364dead4c96867771723469a781,

title = "Design of digital standard cell based on silicon tunnel field-effect transistor",

abstract = "Tunnel FETs was selected as the carrier of digital standard cell design since its excellent characteristics in low power consumption. This experiment contains the principle and characteristic of the Tunnel FETs, and specific standard cell circuit design based on the given model. In this design, we completed several combinational logic cells and sequential logic cells, and did the simulation. From the result of the simulation, we find that TFET devices' speed is slower than MOS device, but the power consumption can reduce to less than 10\% of the same size MOS device. Also, by comparing with the MOS devices, we made the corresponding layout design and DRC rule changes, and as one of the results, the area of TFET device is at least 30\% larger the MOS device.",

keywords = "TFET, layout, powever consumpution, standard cell",

author = "Hang Su and Yiwen Wang and Jipan Huang and Yufei Han and Mingjiang Wang",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 9th IEEE International Conference on Anti-Counterfeiting, Security and Identification, ASID 2015 ; Conference date: 25-09-2015 Through 27-09-2015",

year = "2016",

month = feb,

day = "11",

doi = "10.1109/ICASID.2015.7405663",

language = "英语",

series = "Proceedings of the International Conference on Anti-Counterfeiting, Security and Identification, ASID",

publisher = "IEEE Computer Society",

pages = "66--70",

booktitle = "Proceedings of 2015 IEEE 9th International Conference on Anti-Counterfeiting, Security and Identification, ASID 2015",

address = "美国",

}

Su, H, Wang, Y, Huang, J, Han, Y & Wang, M 2016, Design of digital standard cell based on silicon tunnel field-effect transistor. in Proceedings of 2015 IEEE 9th International Conference on Anti-Counterfeiting, Security and Identification, ASID 2015., 7405663, Proceedings of the International Conference on Anti-Counterfeiting, Security and Identification, ASID, vol. 2016-February, IEEE Computer Society, pp. 66-70, 9th IEEE International Conference on Anti-Counterfeiting, Security and Identification, ASID 2015, Xiamen, China, 25/09/15. https://doi.org/10.1109/ICASID.2015.7405663

Design of digital standard cell based on silicon tunnel field-effect transistor. / Su, Hang; Wang, Yiwen; Huang, Jipan et al.
Proceedings of 2015 IEEE 9th International Conference on Anti-Counterfeiting, Security and Identification, ASID 2015. IEEE Computer Society, 2016. p. 66-70 7405663 (Proceedings of the International Conference on Anti-Counterfeiting, Security and Identification, ASID; Vol. 2016-February).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Design of digital standard cell based on silicon tunnel field-effect transistor

AU - Su, Hang

AU - Wang, Yiwen

AU - Huang, Jipan

AU - Han, Yufei

AU - Wang, Mingjiang

PY - 2016/2/11

Y1 - 2016/2/11

N2 - Tunnel FETs was selected as the carrier of digital standard cell design since its excellent characteristics in low power consumption. This experiment contains the principle and characteristic of the Tunnel FETs, and specific standard cell circuit design based on the given model. In this design, we completed several combinational logic cells and sequential logic cells, and did the simulation. From the result of the simulation, we find that TFET devices' speed is slower than MOS device, but the power consumption can reduce to less than 10% of the same size MOS device. Also, by comparing with the MOS devices, we made the corresponding layout design and DRC rule changes, and as one of the results, the area of TFET device is at least 30% larger the MOS device.

AB - Tunnel FETs was selected as the carrier of digital standard cell design since its excellent characteristics in low power consumption. This experiment contains the principle and characteristic of the Tunnel FETs, and specific standard cell circuit design based on the given model. In this design, we completed several combinational logic cells and sequential logic cells, and did the simulation. From the result of the simulation, we find that TFET devices' speed is slower than MOS device, but the power consumption can reduce to less than 10% of the same size MOS device. Also, by comparing with the MOS devices, we made the corresponding layout design and DRC rule changes, and as one of the results, the area of TFET device is at least 30% larger the MOS device.

KW - TFET

KW - layout

KW - powever consumpution

KW - standard cell

UR - https://www.scopus.com/pages/publications/84962144676

U2 - 10.1109/ICASID.2015.7405663

DO - 10.1109/ICASID.2015.7405663

M3 - 会议稿件

AN - SCOPUS:84962144676

T3 - Proceedings of the International Conference on Anti-Counterfeiting, Security and Identification, ASID

SP - 66

EP - 70

BT - Proceedings of 2015 IEEE 9th International Conference on Anti-Counterfeiting, Security and Identification, ASID 2015

PB - IEEE Computer Society

T2 - 9th IEEE International Conference on Anti-Counterfeiting, Security and Identification, ASID 2015

Y2 - 25 September 2015 through 27 September 2015

ER -

Su H, Wang Y, Huang J, Han Y, Wang M. Design of digital standard cell based on silicon tunnel field-effect transistor. In Proceedings of 2015 IEEE 9th International Conference on Anti-Counterfeiting, Security and Identification, ASID 2015. IEEE Computer Society. 2016. p. 66-70. 7405663. (Proceedings of the International Conference on Anti-Counterfeiting, Security and Identification, ASID). doi: 10.1109/ICASID.2015.7405663

Design of digital standard cell based on silicon tunnel field-effect transistor

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