Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications

Jing Guo; Lei Zhu; Yu Sun; Huiliang Cao; Hai Huang; Tianqi Wang; Chunhua Qi; Rongsheng Zhang; Xuebing Cao; Liyi Xiao; Zhigang Mao

doi:10.1109/TVLSI.2017.2788439

Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications

Jing Guo^*
, Lei Zhu
, Yu Sun
, Huiliang Cao
, Hai Huang
, Tianqi Wang
, Chunhua Qi
, Rongsheng Zhang
, Xuebing Cao
, Liyi Xiao
, Zhigang Mao

^*Corresponding author for this work

School of Astronautics

North University of China
Qiqihar University
China Electronic Product Reliability and Environmental Testing Research Institute
Harbin University of Science and Technology
Harbin Institute of Technology
Shanghai Jiao Tong University

Research output: Contribution to journal › Article › peer-review

105 Scopus citations

Abstract

In this brief, based on upset physical mechanism together with reasonable transistor size, a robust 10T memory cell is first proposed to enhance the reliability level in aerospace radiation environment, while keeping the main advantages of small area, low power, and high stability. Using Taiwan Semiconductor Manufacturing Company 65-nm CMOS commercial standard process, simulations performed in Cadence Spectre demonstrate the ability of the proposed radiation-hardened-by-design 10T cell to tolerate both rightarrow and rightarrow single node upsets, with the increased read/write access time.

Original language	English
Pages (from-to)	991-994
Number of pages	4
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	26
Issue number	5
DOIs	https://doi.org/10.1109/TVLSI.2017.2788439
State	Published - May 2018

Keywords

Access time
aerospace radiation
memory
reliability

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10.1109/TVLSI.2017.2788439

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title = "Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications",

abstract = "In this brief, based on upset physical mechanism together with reasonable transistor size, a robust 10T memory cell is first proposed to enhance the reliability level in aerospace radiation environment, while keeping the main advantages of small area, low power, and high stability. Using Taiwan Semiconductor Manufacturing Company 65-nm CMOS commercial standard process, simulations performed in Cadence Spectre demonstrate the ability of the proposed radiation-hardened-by-design 10T cell to tolerate both rightarrow and rightarrow single node upsets, with the increased read/write access time.",

keywords = "Access time, aerospace radiation, memory, reliability",

author = "Jing Guo and Lei Zhu and Yu Sun and Huiliang Cao and Hai Huang and Tianqi Wang and Chunhua Qi and Rongsheng Zhang and Xuebing Cao and Liyi Xiao and Zhigang Mao",

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year = "2018",

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doi = "10.1109/TVLSI.2017.2788439",

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AU - Guo, Jing

AU - Zhu, Lei

AU - Sun, Yu

AU - Cao, Huiliang

AU - Huang, Hai

AU - Wang, Tianqi

AU - Qi, Chunhua

AU - Zhang, Rongsheng

AU - Cao, Xuebing

AU - Xiao, Liyi

AU - Mao, Zhigang

PY - 2018/5

Y1 - 2018/5

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AB - In this brief, based on upset physical mechanism together with reasonable transistor size, a robust 10T memory cell is first proposed to enhance the reliability level in aerospace radiation environment, while keeping the main advantages of small area, low power, and high stability. Using Taiwan Semiconductor Manufacturing Company 65-nm CMOS commercial standard process, simulations performed in Cadence Spectre demonstrate the ability of the proposed radiation-hardened-by-design 10T cell to tolerate both rightarrow and rightarrow single node upsets, with the increased read/write access time.

KW - Access time

KW - aerospace radiation

KW - memory

KW - reliability

UR - https://www.scopus.com/pages/publications/85041234989

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JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IS - 5

ER -

Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications

Abstract

Keywords

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