Design of an digital lock-in amplifier based on DSP

Chao Fei Tang; Chao Qi; Jing Min Dai; Xiao Gang Sun

Design of an digital lock-in amplifier based on DSP

Chao Fei Tang^*
, Chao Qi
, Jing Min Dai
, Xiao Gang Sun

^*Corresponding author for this work

School of Electrical Engineering and Automation, Harbin Institute of Technology

Research output: Contribution to journal › Article › peer-review

Abstract

The working principle of digital phase-sensitive detector is introduced. A digital lock-in amplifier of wide frequency range is designed. The maxim integrating time is 100 s. The frequency of input weak signal is ranging from 10 Hz to 10 kHz and amplitude is ranging from 100 nV to 100 mV. Every part in the block diagram is described in detail. The measuring dynamic range is expanded by the stage of auto gain ranging. The measuring experimental results show that the relative error is lower than three percent when the sampling count is more than 8192.

Original language	English
Pages (from-to)	241-244
Number of pages	4
Journal	Harbin Gongye Daxue Xuebao/Journal of Harbin Institute of Technology
Volume	37
Issue number	SUPPL. 1
State	Published - May 2005
Externally published	Yes

Keywords

Auto gain ranging
Digital lock-in amplifier
Weak signal detecting

Cite this

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title = "Design of an digital lock-in amplifier based on DSP",

abstract = "The working principle of digital phase-sensitive detector is introduced. A digital lock-in amplifier of wide frequency range is designed. The maxim integrating time is 100 s. The frequency of input weak signal is ranging from 10 Hz to 10 kHz and amplitude is ranging from 100 nV to 100 mV. Every part in the block diagram is described in detail. The measuring dynamic range is expanded by the stage of auto gain ranging. The measuring experimental results show that the relative error is lower than three percent when the sampling count is more than 8192.",

keywords = "Auto gain ranging, Digital lock-in amplifier, Weak signal detecting",

author = "Tang, \{Chao Fei\} and Chao Qi and Dai, \{Jing Min\} and Sun, \{Xiao Gang\}",

year = "2005",

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language = "英语",

volume = "37",

pages = "241--244",

journal = "Harbin Gongye Daxue Xuebao/Journal of Harbin Institute of Technology",

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AU - Tang, Chao Fei

AU - Qi, Chao

AU - Dai, Jing Min

AU - Sun, Xiao Gang

PY - 2005/5

Y1 - 2005/5

N2 - The working principle of digital phase-sensitive detector is introduced. A digital lock-in amplifier of wide frequency range is designed. The maxim integrating time is 100 s. The frequency of input weak signal is ranging from 10 Hz to 10 kHz and amplitude is ranging from 100 nV to 100 mV. Every part in the block diagram is described in detail. The measuring dynamic range is expanded by the stage of auto gain ranging. The measuring experimental results show that the relative error is lower than three percent when the sampling count is more than 8192.

AB - The working principle of digital phase-sensitive detector is introduced. A digital lock-in amplifier of wide frequency range is designed. The maxim integrating time is 100 s. The frequency of input weak signal is ranging from 10 Hz to 10 kHz and amplitude is ranging from 100 nV to 100 mV. Every part in the block diagram is described in detail. The measuring dynamic range is expanded by the stage of auto gain ranging. The measuring experimental results show that the relative error is lower than three percent when the sampling count is more than 8192.

KW - Auto gain ranging

KW - Digital lock-in amplifier

KW - Weak signal detecting

UR - https://www.scopus.com/pages/publications/26644439828

M3 - 文章

AN - SCOPUS:26644439828

SN - 0367-6234

VL - 37

SP - 241

EP - 244

JO - Harbin Gongye Daxue Xuebao/Journal of Harbin Institute of Technology

JF - Harbin Gongye Daxue Xuebao/Journal of Harbin Institute of Technology

IS - SUPPL. 1

ER -

Design of an digital lock-in amplifier based on DSP

Abstract

Keywords

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