Design of a reliable direct error correction pipeline for satellite-borne computer with SEU considered

Reviewing some past research^[1-4], we have come to believe that SEU (single event upset) is the main reason for fault or even failure of satellite-borne computer. Section 1 of the full paper describes the architecture of a pipeline in the Longtium-FT1 microprocessor developed by us, which utilizes a five-stage pipeline and is shown in Fig. 1; then it analyzes the effects of SEU on Longtium-FT1 microprocessor. Section 2 designs the architecture of the direct error correction pipeline, which is shown in the block diagram in Fig. 4. Its core is: ″the pipeline uses the error detection and correction coding (EDAC) technology in register file and uses the triple module redundant (TMR) technology in distributed registers. Fig. 2 shows the structure of EDAC and Fig. 3 shows the structure of TMR with independent clock trees.″ Section 3 implements the Longtium-FT1 microprocessor, whose chip is shown in Fig. 5, and verifies it with some experiments; the experimental results show preliminarily that the Longtium-FT1 microprocessor we designed is reliable and can tolerate SEU up to 300 krads (Si).