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Design of a Mask-Protected Scheme for AES

  • School of Astronautics, Harbin Institute of Technology

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Side-channel attacks exploit leaked power consumption information to crack hardware encryption algorithms. In this paper, an AES encryption and decryption module with masking has been implemented using Verilog HDL. The most critical nonlinear S-box substitution adopts an implementation method based on finite fields. The analysis of results shows that, compared to algorithms without masking, this method can effectively counter side-channel attacks and enhance the security of hardware encryption implementations.

Original languageEnglish
Title of host publication2024 IEEE Academic International Symposium on Optoelectronics and Microelectronics Technology, AISOMT 2024
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages438-443
Number of pages6
ISBN (Electronic)9798331542283
DOIs
StatePublished - 2024
Externally publishedYes
Event2024 IEEE Academic International Symposium on Optoelectronics and Microelectronics Technology, AISOMT 2024 - Harbin, China
Duration: 21 Nov 202422 Nov 2024

Publication series

Name2024 IEEE Academic International Symposium on Optoelectronics and Microelectronics Technology, AISOMT 2024

Conference

Conference2024 IEEE Academic International Symposium on Optoelectronics and Microelectronics Technology, AISOMT 2024
Country/TerritoryChina
CityHarbin
Period21/11/2422/11/24

Keywords

  • AES
  • Hardware
  • Masking
  • Side-channel attacks

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