Design of a cyclic column-parallel ADC for Monolithic Active Pixel Sensor

Y. S. Wang; Y. Wen; W. Lu; H. Wang; Y. Wang; F. Fu; Y. Tian; W. Zhou; H. Yang; J. Wang; C. Zhao

doi:10.1088/1748-0221/15/02/C02004

Design of a cyclic column-parallel ADC for Monolithic Active Pixel Sensor

Y. S. Wang
, Y. Wen
, W. Lu
, H. Wang
, Y. Wang
, F. Fu
, Y. Tian
, W. Zhou
, H. Yang
, J. Wang
, C. Zhao^*

^*Corresponding author for this work

School of Astronautics

Harbin Institute of Technology
Chinese Academy of Sciences
University of Chinese Academy of Sciences

Research output: Contribution to journal › Article › peer-review

2 Scopus citations

Abstract

This paper describes a 5-bit cyclic column-parallel ADC for Monolithic Active Pixel Sensor. The column-parallel ADC combines the dedicated sample phase and the signal conversion phase into a single phase. Moreover, it has a high tolerance to the offset of the comparators in the ADC by generating 1.5 bit in every stage. Each column-parallel ADC covers a small area of 100 μm × 200 μm, consumes 4.5 mW at 3.3 V supply and provides the sampling rate of 10 MS/s with the dynamic range of 1000 mV. The results show that the ADC has a signal-to-noise and distortion ratio (SNDR) of 28.47 dB. Its DNL and INL are -0.039/0.055 LSB and -0.048/0.095 LSB, respectively.

Original language	English
Article number	C02004
Journal	Journal of Instrumentation
Volume	15
Issue number	2
DOIs	https://doi.org/10.1088/1748-0221/15/02/C02004
State	Published - 4 Feb 2020

Keywords

Analogue electronic circuits
Particle tracking detectors
Pixelated detectors and associated VLSI electronics
VLSI circuits

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10.1088/1748-0221/15/02/C02004

Cite this

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title = "Design of a cyclic column-parallel ADC for Monolithic Active Pixel Sensor",

abstract = "This paper describes a 5-bit cyclic column-parallel ADC for Monolithic Active Pixel Sensor. The column-parallel ADC combines the dedicated sample phase and the signal conversion phase into a single phase. Moreover, it has a high tolerance to the offset of the comparators in the ADC by generating 1.5 bit in every stage. Each column-parallel ADC covers a small area of 100 μm × 200 μm, consumes 4.5 mW at 3.3 V supply and provides the sampling rate of 10 MS/s with the dynamic range of 1000 mV. The results show that the ADC has a signal-to-noise and distortion ratio (SNDR) of 28.47 dB. Its DNL and INL are -0.039/0.055 LSB and -0.048/0.095 LSB, respectively.",

keywords = "Analogue electronic circuits, Particle tracking detectors, Pixelated detectors and associated VLSI electronics, VLSI circuits",

author = "Wang, \{Y. S.\} and Y. Wen and W. Lu and H. Wang and Y. Wang and F. Fu and Y. Tian and W. Zhou and H. Yang and J. Wang and C. Zhao",

note = "Publisher Copyright: {\textcopyright} 2020 IOP Publishing Ltd and Sissa Medialab.",

year = "2020",

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day = "4",

doi = "10.1088/1748-0221/15/02/C02004",

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TY - JOUR

T1 - Design of a cyclic column-parallel ADC for Monolithic Active Pixel Sensor

AU - Wang, Y. S.

AU - Wen, Y.

AU - Lu, W.

AU - Wang, H.

AU - Wang, Y.

AU - Fu, F.

AU - Tian, Y.

AU - Zhou, W.

AU - Yang, H.

AU - Wang, J.

AU - Zhao, C.

PY - 2020/2/4

Y1 - 2020/2/4

N2 - This paper describes a 5-bit cyclic column-parallel ADC for Monolithic Active Pixel Sensor. The column-parallel ADC combines the dedicated sample phase and the signal conversion phase into a single phase. Moreover, it has a high tolerance to the offset of the comparators in the ADC by generating 1.5 bit in every stage. Each column-parallel ADC covers a small area of 100 μm × 200 μm, consumes 4.5 mW at 3.3 V supply and provides the sampling rate of 10 MS/s with the dynamic range of 1000 mV. The results show that the ADC has a signal-to-noise and distortion ratio (SNDR) of 28.47 dB. Its DNL and INL are -0.039/0.055 LSB and -0.048/0.095 LSB, respectively.

AB - This paper describes a 5-bit cyclic column-parallel ADC for Monolithic Active Pixel Sensor. The column-parallel ADC combines the dedicated sample phase and the signal conversion phase into a single phase. Moreover, it has a high tolerance to the offset of the comparators in the ADC by generating 1.5 bit in every stage. Each column-parallel ADC covers a small area of 100 μm × 200 μm, consumes 4.5 mW at 3.3 V supply and provides the sampling rate of 10 MS/s with the dynamic range of 1000 mV. The results show that the ADC has a signal-to-noise and distortion ratio (SNDR) of 28.47 dB. Its DNL and INL are -0.039/0.055 LSB and -0.048/0.095 LSB, respectively.

KW - Analogue electronic circuits

KW - Particle tracking detectors

KW - Pixelated detectors and associated VLSI electronics

KW - VLSI circuits

UR - https://www.scopus.com/pages/publications/85081246416

U2 - 10.1088/1748-0221/15/02/C02004

DO - 10.1088/1748-0221/15/02/C02004

M3 - 文章

AN - SCOPUS:85081246416

SN - 1748-0221

VL - 15

JO - Journal of Instrumentation

JF - Journal of Instrumentation

IS - 2

M1 - C02004

ER -

Design of a cyclic column-parallel ADC for Monolithic Active Pixel Sensor

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Keywords

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