TY - GEN
T1 - Design methodology for electron-trap memory cells
AU - Bingxi, Li
AU - Chunhong, Chen
PY - 2008
Y1 - 2008
N2 - In order to further reduce the feature size of semiconductor devices, the field of single-electronics has come of age. Single electron tunneling (SET) technology uses a single or few electrons to implement various analog and digital applications. Memory design is such a typical example. In this paper, we present a design methodology by discussing the parameter selection and reliability analysis for SET-based electron-trap memory cells. It is shown that the parameter selection is important for correct logic operation of these memory cells as well as their reliability improvement. All the results are verified by the SIMION simulator.
AB - In order to further reduce the feature size of semiconductor devices, the field of single-electronics has come of age. Single electron tunneling (SET) technology uses a single or few electrons to implement various analog and digital applications. Memory design is such a typical example. In this paper, we present a design methodology by discussing the parameter selection and reliability analysis for SET-based electron-trap memory cells. It is shown that the parameter selection is important for correct logic operation of these memory cells as well as their reliability improvement. All the results are verified by the SIMION simulator.
UR - https://www.scopus.com/pages/publications/55349131346
U2 - 10.1109/NANO.2008.15
DO - 10.1109/NANO.2008.15
M3 - 会议稿件
AN - SCOPUS:55349131346
SN - 9781424421046
T3 - 2008 8th IEEE Conference on Nanotechnology, IEEE-NANO
SP - 22
EP - 24
BT - 2008 8th IEEE Conference on Nanotechnology, IEEE-NANO
T2 - 2008 8th IEEE Conference on Nanotechnology, IEEE-NANO
Y2 - 18 August 2008 through 21 August 2008
ER -