TY - GEN
T1 - Design and verification of SRAM self-detection repair based on ECC and BISR circuit
AU - Zhang, Yanqing
AU - Piao, Yinghun
AU - Huo, Mingxue
AU - Wang, Tianqi
AU - Ma, Guoliang
AU - Liu, Chaoming
AU - Ma, Jianning
AU - Guo, Kairui
AU - Qi, Chunhua
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/7
Y1 - 2019/7
N2 - In the space radiation environment, the chip in the spacecraft is susceptible to radiation effects, which leading to the errors of the device. Therefore, the detection and repair of the errors is particularly important. Aiming at the soft and hard errors of memory cell caused by single event effect in space radiation environment, a memory architecture based on ECC circuit and BISR circuit is proposed to detect errors online, distinguish between soft and hard errors and repair them, so as to reduce the accumulation of errors. And the memory structure uses repair circuit and redundant memory to repair soft errors and hard errors respectively. The simulation results show that in normal read-write mode, the proposed memory structure not only can repair soft errors, but also can repair hard errors, and can detect unrepairable hard errors. It means that the proposed method is effective. when the memory size is 39 x 64K, the area of the ECC and the BIRA circuit is about 13.95% of the entire memory chip.
AB - In the space radiation environment, the chip in the spacecraft is susceptible to radiation effects, which leading to the errors of the device. Therefore, the detection and repair of the errors is particularly important. Aiming at the soft and hard errors of memory cell caused by single event effect in space radiation environment, a memory architecture based on ECC circuit and BISR circuit is proposed to detect errors online, distinguish between soft and hard errors and repair them, so as to reduce the accumulation of errors. And the memory structure uses repair circuit and redundant memory to repair soft errors and hard errors respectively. The simulation results show that in normal read-write mode, the proposed memory structure not only can repair soft errors, but also can repair hard errors, and can detect unrepairable hard errors. It means that the proposed method is effective. when the memory size is 39 x 64K, the area of the ECC and the BIRA circuit is about 13.95% of the entire memory chip.
KW - BISR
KW - ECC
KW - Hard error
KW - Single event effect
KW - Soft error
UR - https://www.scopus.com/pages/publications/85082598902
U2 - 10.1109/IPFA47161.2019.8984845
DO - 10.1109/IPFA47161.2019.8984845
M3 - 会议稿件
AN - SCOPUS:85082598902
T3 - Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
BT - 26th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 26th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2019
Y2 - 2 July 2019 through 5 July 2019
ER -