@inproceedings{e99dcb0ea4ee4e03b2113df24b1a3748,
title = "Design and realization of reed-solomon codec based on FPGA technique",
abstract = "In this paper, we present a design and realization of RS(255, 223) codec targeted for an image transmission system. The low-complexity pipelined RS(255, 223) decoder with the Berlekamp-Massey (BM) linear feedback shift register (LFSR) algorithm used is able to operate at a clock frequency of 120MHz and has a data throughout rate of 960 Mb/s. Simulations displayed by Signal Tap II software which derives the actual signals run inside the Cyclone II FPGA manufactured by Altera certificate the analysis of each part of the codec. Also, the BER performance of RS(255, 223) simulated by Matlab is shown at the end of the paper.",
keywords = "RS codec, RS decoder, Simulation",
author = "Jiabin You and Shaochuan Wu",
year = "2011",
doi = "10.1109/MEC.2011.6025902",
language = "英语",
isbn = "9781612847221",
series = "Proceedings 2011 International Conference on Mechatronic Science, Electric Engineering and Computer, MEC 2011",
pages = "2086--2089",
booktitle = "Proceedings 2011 International Conference on Mechatronic Science, Electric Engineering and Computer, MEC 2011",
note = "2011 International Conference on Mechatronic Science, Electric Engineering and Computer, MEC 2011 ; Conference date: 19-08-2011 Through 22-08-2011",
}