Design and implementation of concatenated encoder

Yu xin You; Jin xiang Wang; Xiu ri Piao; Feng chang Lai; Yi zheng Ye

Design and implementation of concatenated encoder

Yu xin You^*
, Jin xiang Wang
, Xiu ri Piao
, Feng chang Lai
, Yi zheng Ye

^*Corresponding author for this work

Electrical Eng. Limited Company

Research output: Contribution to conference › Paper › peer-review

1 Scopus citations

Abstract

We presented a concatenated encoder that has very widely applications in DVB, HDTV and satellite communication systems. It was mainly composed of punctured convolutional encoder, convolutional interleaver, and Reed-Solomon encoder. In the convolutional interleaver, an over-clocking scheme is employed to guarantee the speed limits. Furthermore, a finite field multiplier of composite fields was adapted to optimize area and power in RS encoder, which reduced the area near to one half compared to the conventional RS (204,188) encoder. The proposed concatenated encoder has about 3700 gates except RAM model and it has good compliance with EN300 421.

Original language	English
Pages	444-447
Number of pages	4
State	Published - 2001
Externally published	Yes
Event	4th International Conference on ASIC Proceedings - Shanghai, China Duration: 23 Oct 2001 → 25 Oct 2001

Conference

Conference	4th International Conference on ASIC Proceedings
Country/Territory	China
City	Shanghai
Period	23/10/01 → 25/10/01

Cite this

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title = "Design and implementation of concatenated encoder",

abstract = "We presented a concatenated encoder that has very widely applications in DVB, HDTV and satellite communication systems. It was mainly composed of punctured convolutional encoder, convolutional interleaver, and Reed-Solomon encoder. In the convolutional interleaver, an over-clocking scheme is employed to guarantee the speed limits. Furthermore, a finite field multiplier of composite fields was adapted to optimize area and power in RS encoder, which reduced the area near to one half compared to the conventional RS (204,188) encoder. The proposed concatenated encoder has about 3700 gates except RAM model and it has good compliance with EN300 421.",

author = "You, \{Yu xin\} and Wang, \{Jin xiang\} and Piao, \{Xiu ri\} and Lai, \{Feng chang\} and Ye, \{Yi zheng\}",

year = "2001",

language = "英语",

pages = "444--447",

note = "4th International Conference on ASIC Proceedings ; Conference date: 23-10-2001 Through 25-10-2001",

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TY - CONF

T1 - Design and implementation of concatenated encoder

AU - You, Yu xin

AU - Wang, Jin xiang

AU - Piao, Xiu ri

AU - Lai, Feng chang

AU - Ye, Yi zheng

PY - 2001

Y1 - 2001

N2 - We presented a concatenated encoder that has very widely applications in DVB, HDTV and satellite communication systems. It was mainly composed of punctured convolutional encoder, convolutional interleaver, and Reed-Solomon encoder. In the convolutional interleaver, an over-clocking scheme is employed to guarantee the speed limits. Furthermore, a finite field multiplier of composite fields was adapted to optimize area and power in RS encoder, which reduced the area near to one half compared to the conventional RS (204,188) encoder. The proposed concatenated encoder has about 3700 gates except RAM model and it has good compliance with EN300 421.

AB - We presented a concatenated encoder that has very widely applications in DVB, HDTV and satellite communication systems. It was mainly composed of punctured convolutional encoder, convolutional interleaver, and Reed-Solomon encoder. In the convolutional interleaver, an over-clocking scheme is employed to guarantee the speed limits. Furthermore, a finite field multiplier of composite fields was adapted to optimize area and power in RS encoder, which reduced the area near to one half compared to the conventional RS (204,188) encoder. The proposed concatenated encoder has about 3700 gates except RAM model and it has good compliance with EN300 421.

UR - https://www.scopus.com/pages/publications/0035721165

M3 - 论文

AN - SCOPUS:0035721165

SP - 444

EP - 447

T2 - 4th International Conference on ASIC Proceedings

Y2 - 23 October 2001 through 25 October 2001

ER -

Design and implementation of concatenated encoder

Abstract

Conference

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