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Demodulation of 8PSK signal with gardner bit synchronization using FPGA

  • Harbin Institute of Technology

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, a new method of bit synchronization of 8PSK signal based on Gardner algorithm is proposed. When using Gardner bit synchronization, some improvements must be made to accommodate the demodulation of the 8PSK signal. Firstly, a detailed analysis of mathematical model for the Gardner bit synchronization is made, and then the algorithm simulation is accomplished on Quartus and ModelSim joint platform by Verilog HDL. The implement result by FPGA shows the feasibility and the stability of the proposed algorithms.

Original languageEnglish
Title of host publicationCommunications, Signal Processing, and Systems - Proceedings of the 2017 International Conference on Communications, Signal Processing, and Systems
EditorsQilian Liang, Min Jia, Jiasong Mu, Wei Wang, Xuhong Feng, Baoju Zhang
PublisherSpringer Verlag
Pages661-668
Number of pages8
ISBN (Print)9789811065705
DOIs
StatePublished - 2019
Event6th International Conference on Communications, Signal Processing, and Systems, CSPS 2017 - Harbin, China
Duration: 14 Jul 201716 Jul 2017

Publication series

NameLecture Notes in Electrical Engineering
Volume463
ISSN (Print)1876-1100
ISSN (Electronic)1876-1119

Conference

Conference6th International Conference on Communications, Signal Processing, and Systems, CSPS 2017
Country/TerritoryChina
CityHarbin
Period14/07/1716/07/17

Keywords

  • 8PSK
  • FPGA
  • Gardner bit synchronization

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